1. Field of the Invention
The present invention relates to integration circuit fabrication, and more particularly to methods of fabricating integrated circuits with reduced pitch.
2. Description of Related Art
Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, so as to increase the density of the individual components and consequently enhance the functionality of an integrated circuit. The minimum pitch on an integrated circuit (the minimum distance between the same points of two adjacent structures of the same type, e.g., two adjacent gate conductors) is often used as a representative measure of the circuit's density.
Increases in circuit density often are limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is related to its resolution capacity.
The sum of the minimum feature width and minimum space width producible with a given piece of photolithographic equipment is the minimum pitch that the piece of equipment can produce. The minimum feature width can often times be approximately equal to the minimum space width, so the minimum pitch that can be produced with a given piece of photolithographic equipment is approximately equal to double the minimum feature width that it can produce.
Some attempts have been made to try and reduce the pitch of an integrated circuit device below that of the minimum pitch produced lithographically, but these methods are difficult to control and show varying results.
In view of the drawbacks of the prior methods, it is necessary to provide a method that can reduce the pitch in a device below that producible by the lithographic process.